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PD - 95575
Logic-Level Gate Drive Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 175C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Description
l l
IRL1004SPBF IRL1004LPbF
HEXFET(R) Power MOSFET
D
VDSS = 40V
G S
RDS(on) = 0.0065 ID = 130A
Fifth Generation HEXFET(R) power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL1004L) is available for lowprofile application.
D2Pak IRL1004S
TO-262 IRL1004L
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
130 92 520 3.8 200 1.3 16 700 78 20 5.0 -55 to + 175 300 (1.6mm from case)
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)*
Typ.
--- ---
Max.
0.75 40
Units
C/W
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1
07/19/04
IRL1004S/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS Ciss Coss Crss
Min. 40 --- 1.0 63 --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. Max. Units Conditions --- --- V VGS = 0V, ID = 250A 0.04 --- V/C Reference to 25C, ID = 1mA 0.0065 VGS = 10V, ID = 78A 0.009 VGS = 4.5V, ID = 65A --- V VDS = VGS, ID = 250A S VDS = 25V, ID = 78A 25 VDS = 40V, VGS = 0V A --- 250 VDS = 32V, VGS = 0V, TJ = 150C --- 100 VGS = 16V nA --- -100 VGS = -16V --- 100 ID = 78A --- 32 nC VDS = 32V --- 43 VGS = 4.5V, See Fig. 6 and 13 16 --- VDD = 20V, 210 --- ID = 78A, 25 --- ns RG = 2.5, 14 --- RD = 0.18, See Fig. 10 Between lead, 7.5 nH --- and center of die contact 5330 --- VGS = 0V 1480 --- pF VDS = 25V 320 --- = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 130 showing the A G integral reverse --- --- 520 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 78A, VGS = 0V --- 78 120 ns TJ = 25C, IF = 78A --- 180 270 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Pulse width 300s; duty cycle 2%.
Calculated continuous current based on maximum allowable junction temperature; for recommended current-handing of the package refer to Design Tip # 93-4 Uses IRL1004 data and test conditions
Starting TJ = 25C, L = 0.23mH
RG = 25, I AS = 78A. (See Figure 12)
ISD 78A, di/dt 370A/s, VDD V(BR)DSS,
TJ 175C
* When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRL1004S/LPbF
10000
VGS 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V TOP
1000
I D , Drain-to-Source Current (A)
1000
I D , Drain-to-Source Current (A)
VGS 15V 10V 7.0V 5.5V 4.5V 4.0V 3.5V BOTTOM 2.7V TOP
100
100
10
10
2.7V
1
2.7V
20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 0.1
1 0.1
20s PULSE WIDTH TJ = 175 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.5
I D , Drain-to-Source Current (A)
TJ = 25 C
100
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 130A
2.0
TJ = 175 C
1.5
10
1.0
1
0.5
0.1 2.0
V DS = 50V 20s PULSE WIDTH 3.0 4.0 5.0 6.0 7.0 8.0 9.0
0.0 -60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRL1004S/LPbF
10000
VGS , Gate-to-Source Voltage (V)
8000
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
12
ID = 78 A
VDS = 32V VDS = 20V
10
C, Capacitance (pF)
6000
Ciss
8
6
4000
Coss
4
2000
Crss
0 1 10 100
2
0 0 30 60 90
FOR TEST CIRCUIT SEE FIGURE 13
120 150 180
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
10000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
ID , Drain Current (A)
100
TJ = 175 C
1000 10us 100us 1ms 10 10ms
10
100
TJ = 25 C
1
0.1 0.0
V GS = 0 V
0.5 1.0 1.5 2.0 2.5 3.0
1 1
TC = 25 C TJ = 175 C Single Pulse
10 100
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRL1004S/LPbF
140
LIMITED BY PACKAGE
120
VDS VGS RG
RD
D.U.T.
+
ID , Drain Current (A)
100 80 60 40 20 0
-V DD
10V
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
VDS 90%
25
50
75
100
125
150
175
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
1
Thermal Response (Z thJC)
D = 0.50
0.20 0.1 0.10 0.05 0.02 0.01 PDM t1 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 t2
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRL1004S/LPbF
L VDS D.U.T. RG + 4.5 V
EAS , Single Pulse Avalanche Energy (mJ)
1800
TOP BOTTOM
1500
ID 32A 55A 78A
VDD
IAS tp
0.01
1200
900
Fig 12a. Unclamped Inductive Test Circuit
600
300
V(BR)DSS tp VDD VDS
0 25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
4.5 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit
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IRL1004S/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-channel HEXFET(R) Power MOSFETs
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IRL1004S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T H IS IS AN IR F 530S WIT H LOT CODE 8024 AS S E MB L E D ON WW 02, 2000 IN T H E AS S E MB LY LINE "L" Note: "P" in as s embly line pos ition indicates "L ead-F ree" INT E RNAT IONAL RE CT IF IE R LOGO PART NUMB E R F 530S DAT E CODE YE AR 0 = 2000 WE E K 02 LINE L
AS S E MB L Y L OT CODE
OR
INT ERNAT IONAL RE CT IF IER LOGO AS S EMB LY L OT CODE PART NU MB E R F 530S DAT E CODE P = DE S IGNAT E S L E AD-F RE E PRODUCT (OPT IONAL) YEAR 0 = 2000 WEE K 02 A = AS S E MB L Y S IT E CODE
8
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IRL1004S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPLE: THIS IS AN IRL 3103L LOT CODE 1789 AS S EMBL ED ON WW 19, 1997 IN THE AS S E MB LY L INE "C" Note: "P" in as s embly line pos ition indicates "L ead-F ree" INT ERNATIONAL RE CTIF IE R L OGO AS S EMBLY LOT CODE PART NUMBE R
DAT E CODE YE AR 7 = 1997 WE EK 19 LINE C
OR
INT ERNAT IONAL RECT IF IER L OGO AS S EMBL Y L OT CODE PART NUMB ER DAT E CODE P = DES IGNAT E S LEAD-F RE E PRODUCT (OPT IONAL) YE AR 7 = 1997 WE EK 19 A = AS S EMBL Y S IT E CODE
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IRL1004S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197) MAX.
26.40 (1.039) 24.40 (.961) 3
4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/04
10
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